1. Field of the Invention
The present invention is generally directed to semiconductor memories, and more particularly, to the development of memory cells which can be easily integrated with high performance logic technologies.
2. State of the Art
Those skilled in the art appreciate the desirability of embedding memory technology such as dynamic random access memories (DRAMs), static random access memories (SRAMs), read-only memories (ROMs), electrically erasable programmable read-only memories (EEPROMs), and flash EEPROMs into high performance logic technologies. However, at present, only technologies such as SRAM and ROM are straightforward to integrate into high performance logic technologies. Technologies, such as EEPROM and DRAM technologies are highly dedicated to their specific needs, and are very complex, rendering them unsuitable for straightforward, easy integration into high performance logic technologies.
For example, EEPROM technology is typically implemented using one of four basic cell types: (1) the one transistor stacked-gate flash EEPROM cell; (2) the one and one half transistor split-gate flash EEPROM cell; (3) the double-gate two transistor EEPROM cell; and (4) cells which use edges for control or select gates. There have also been proposals regarding flash memory cells which form self-aligned trenches at the edge of a partially formed stack-gate structure. However, each of these technologies suffers drawbacks which inhibits their straightforward, easy integration into high performance logic technologies.
FIG. 1A shows a typical one transistor stacked-gate flash EEPROM cell. Stacked-gate flash EEPROM cells are available from Intel Corp. and Advanced Micro Devices Corp. (e.g., the Intel E28F016SA 16 Mbit flash memory and the AMD AM29F016 16 Mbit flash memory), having basic cell sizes of approximately 6 and 7 times the minimum feature size (f) squared (i.e., f.sup.2), respectively. However, these cells possess a very complex source-drain region which requires as many as four ion implants. These submicron cells are subject to punch through, premature breakdown at the drain, and various read disturb problems. In addition, the cells are susceptible to over erase, which can lead to a permanently turned-on device. These cells are also difficult to downward scale, because high voltages are required for the erase and program functions. Erasure is performed by taking an extended source diffused region to a high positive value to pull electrons from the floating gate by Fowler-Nordheim (FN) tunneling to make the floating gate more positive. The erase function is performed by lowering the floating gate threshold voltage V.sub.T, while programming is accomplished by applying high voltage to the drain and to the control gate formed with a second polysilicon layer (i.e., poly 2) to inject hot electrons from a channel near the drain onto the floating gate to raise the threshold voltage. That is, programming is achieved using hot electron injection by applying high voltage to the control gate. The high voltage (e.g., approximately 12 volts) requires inclusion of separate high voltage transistors.
The exemplary FIG. 1 cell involves using two levels of polysilicon. Typical products use a NOR configuration, where each cell is configured with a bit line (BL) connection to the drain, a poly 2 control line (CL) or word line (WL), and a diffused source line (SL). The high voltages required for this device require building separate high voltage transistors which may have longer distances between the source of drain diffusion (i.e., longer L.sub.eff) and thicker gate oxides, thereby adding to the overall size of a memory device implemented with these cells.
A one and one-half transistor split-gate flash EEPROM, as shown in FIG. 1B, avoids the over erase problem described with respect to the stacked-gate flash EEPROM cell, but is a larger cell size than the stacked gate. For a split-gate cell using modern shallow trench isolation (STI), an n+ source line self-aligned to the poly, self-aligned tungsten plug contacts, and conservative poly 1 to poly 2 alignment tolerances, a typical cell area can be on the order of approximately 10 f.sup.2. Lower n+ source regions may be created in the substrate by etching the oxide in an STI region down to the substrate. The poly 2 layer and a resist mask are used to protect other shallow trench isolation (STI) regions during etching.
A double-gate two transistor EEPROM cell is shown in FIG. 1C, and includes a separate select transistor to permit erasure of individual cells. Such a cell is, for example, available from Atmel in its AT17C128 128 k serial EEPROM, which has a cell area of approximately 17 f.sup.2 for 1.0 micron rules. The cell is relatively large and is not used in flash EEPROMs.
FIG. 1D illustrates an exemplary cell which uses polysilicon edges for control of select gates. For example, exemplary versions of this cell use closely spaced polysilicon edges for voltage coupling. Although the cells are smaller than the cells discussed previously, they are very complex as reflected, for example, in the Sandisk 35 bit triple-polysilicon flash EEPROM, which is approximately 5 f.sup.2 in cell area using 0.6 micron rules. Because of their complexity, they are unsuited to integration in high performance logic technology.
FIG. 1E shows an exemplary flash memory cell described in a document entitled "A 0.24 .mu.m 2 Well Process with 0.18 .mu.m Width Isolation and 3-D Interpoly Dielectric Films for 1-Gb Flash Memories", by Takashi Kobayashi et al, 1997 IEDM, page 275. Again, the process of producing such a cell is complex, and impractical for integration into high performance logic technology.
Because numerous applications exist for integrating flash EEPROM technology with high performance complementary metal oxide semiconductor (CMOS) logic devices (e.g., microprocessors), the development of such a technology would be highly desirable. For example, the applications for such an integrated technology include software updates, storing identification codes, system reconfiguration in the field, look-up tables, manufacturing codes, nonvolatile data storage, smart cards which use flash embedded memory, prototyping, and various programmable logic devices and field programmable gate arrays.
Known process technologies do not lend themselves to easy integration of commodity flash EEPROM cells with logic devices, such as high performance CMOS devices. That is, known processes, including processes as described in a document entitled "EEPROM/Flash Sub 3.0V Drain-Source Bias Hot Carrier Rating", by J. D. Bude et al., 1995 IEDM, page 989 and in a document entitled "Secondary Electron Flash--A High Performance Low Power Flash Technology for 0.25 .mu.m and Below, by J. D. Bude et al., 1997, IEDM page 279, do not sufficiently simplify the flash EEPROM cell and fabrication process to permit straightforward integration into conventional high performance logic processes. In these documents, structural properties of submicron stacked gate EEPROM devices are disclosed which yield devices that can be programmed at low voltages. The properties are: (1) thin tunneling oxides (e.g., in a range of approximately 60 angstroms (.ANG.)-100 .ANG.); (2) heavily-doped shallow n+ junctions with boron halo implants, giving abrupt junctions; and (3) a negative substrate bias.
In addition to process compatibility problems, scaling EEPROM technology into the 0.25 .mu.m regime and below, as is used on typical high performance logic processes, has not been realized. Those skilled in the art have suggested that scaling EEPROM devices is subject to physical limits which may inhibit a reduction in cell size (see, for example, "Nonvolatile Semiconductor Memory Technology", by William D. Brown and Joe E. Brewer, IEEE, Press 1998, page 130). Given the wide applicability of flash EEPROM technology, it would be desirable to avoid the process compatibility problems associated with integrating typical cell designs with conventional logic devices by developing a cell which can be easily integrated into high performance logic processes.